A Case for Instruction Subset Architectures (ISA): Guaranteeing Functionality in High Defect Rate Technologies

As we move towards the end of the technology roadmap, and potentially to newer technology flavors besides conventional CMOS, transistor defect rates are expected to increase significantly. Till recently, industry has dealt with defects (including both manufacturing defects and defects at run-time) using conservative approaches discarding non-functioning chips at test time and extensive guardbanding. With increasing defect rates, however, these conservative approaches will become untenable, resulting in prohibitive yield and performance loss. This is the challenge that Instruction Subset Architectures (ISA) try to address — how do we design and architect processors, either singleor multi-core, that degrade gracefully with increasing defect rates. More specifically, how do we guarantee functional correctness, possibly at the expense of a performance penalty, in a system where each core has one or more faulty transistors. The challenge of graceful degradation has been extensively addressed for the memory sub-system — as illustrated in Figure 1, spare rows/columns and error-coding techniques can be used in caches to protect can against a relatively large number of transistor failures. In the worst-case, faulty bit cells reduce capacity and impact performance, but do not impact functionality. However, the same cannot be said for the core logic. For the most part, extant techniques to deal with faulty transistors in processing cores involve fully disabling cores. With increased defect rates, however, the likelihood that each core has at least one faulty transistor will grow to a point where disabling cores will result in unacceptable yield loss. Any fault-tolerant design methodology depends on an assumed fault model. However, existing fault models focus on the transistoror gate-level abstractions, which we find are inadequate to meet the challenges in designing gracefully degrading processors. Instead, in this paper, we make a case for the use of instruction-set level fault models that make the impact of transistor faults explicit at higher levels of abstraction. As a first step in this direction, we propose a simple yet powerful high-level fault model to aid in the design of gracefully degrading processors, which we call the instruction subset fault (IS) model. The IS fault model sets the Figure 1: Cache yield degrades gracefully with increasing bit faults [1]. Analogously, the instruction subset (IS) fault model identifies the percentage of functioning instructions in the ISA with increasing defects instead of assuming that every transistor in the core logic is a single point of failure.